Sample Waveforms for PLL4XD0.VHD

Sample behavioral waveforms for design file PLL4XD0.VHD

The following waveforms show the behavior of altpll megafunction for the chosen set of parameters in design PLL4XD0.VHD. The design PLL4XD0.VHD has Cyclone III AUTO pll configured in NORMAL mode The primary clock input to the PLL is INCLK0, with clock period 20000 ps. Output port LOCKED will go high when the PLL locks to the input clock.

Fig. 1 : Wave showing NORMAL mode operation.